Integrated circuit including trench capacitor

ABSTRACT

A method of manufacturing a capacitor including the operations of etching a plurality of primary trenches into a first region of a substrate, the primary trenches extending in a first direction, etching a plurality of secondary trenches into the first region of the substrate, the secondary trenches extending in a second direction other than the first direction, with the adjacent secondary trenches and adjacent primary trenches jointly defining an island structure having an upper surface that is recessed relative to an upper surface a surrounding substrate, and depositing a series of film pairs including a dielectric layer and a conductive layer.

PRIORITY STATEMENT

This application claims priority from U.S. Prov. Pat. Appl. No.62/734,644, filed Sep. 21, 2018, and is a divisional application of andclaims priority from U.S. patent application Ser. No. 16/518,257, filedJul. 22, 2019, which was issued as U.S. Pat. No. 11,329,125, on May 10,2022, each of which is incorporated by reference in its entirety.

BACKGROUND

Integrated circuits frequently include capacitors in order to performdata storage in memory chips or to regulate timing of elements in anintegrated circuit. Capacitors have high aspect ratios, such as via-likecapacitors that are etched deep into a dielectric medium, or areelongated, such as trench capacitors. A capacitor's storage increaseswhen the surface area of the capacitor plates increases, the distancebetween the capacitor plates decreases, and/or the permittivity of thedielectric material between capacitor plates increases. The cost ofmanufacturing an integrated circuit is reduced by reducing overallintegrated circuit layout area, in order to fit more circuit dies on amanufacturing substrate. Overall circuit layout area is reduced byreducing layout area of individual circuit components, includingcapacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is an integrated circuit having capacitors in accordance withsome embodiments.

FIG. 2 is a plan view of linear trench capacitors in an integratedcircuit according to some embodiments.

FIG. 3 is a plan view of a trench capacitor having an open cross-hatchedstructure, according to some embodiments.

FIGS. 4A and 4B are plan views of trench capacitors having at least someclosed cross-hatched structure, according to some embodiments.

FIG. 5 is a cross-sectional view of a trench capacitor having across-hatched structure, according to some embodiments.

FIG. 6 is a cross-sectional view of a trench capacitor having across-hatched structure, according to some embodiments.

FIGS. 7A and 7B are plan views of capacitors having a field and islandstructure, according to some embodiments.

FIG. 8 is a flow diagram of a method of making a trench capacitor havinga cross-hatched structure, according to some embodiments.

FIG. 9 is a cross-sectional diagram of a capacitor, according to someembodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components, values, operations, materials,arrangements, and the like, are described below to simplify the presentdisclosure. These are, of course, merely examples and are not intendedto be limiting. Other components, values, operations, materials,arrangements, and the like, are contemplated. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The term “on”indicates that two layers or portions of an object are either in directcontact, or that one is “above” another (as viewed in drawings of theobject) with intervening layers or objects. The term “directly on” isused to refer to two objects or layers that at least partially in directcontact with no intervening objects or layers at the point of directcontact. The spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

Electrical circuits contain assemblies of basic components such astransistors, resistors, capacitors, and inductors. The function of anelectrical circuit depends on the content and arrangement of the variousbasic components. Integrated electrical circuits include components withparticular structural designs that allow the manufacture and integrationof circuit components on a single semiconductor substrate. Capacitorsare found in many integrated circuits and are used for storingelectrical charge. The charging and discharging of a capacitor isrelevant to the timing of circuit performance, the storage andpreservation of information in a memory circuit, or the protecting of anintegrated circuit from electrical damage. Capacitors for storing dataare found in dynamic random access memory (DRAM) integrated circuitapplications, in some embodiments.

FIG. 1 is a schematic diagram of an integrated circuit 100 in asubstrate 102, the circuit having a via capacitor 104 and a trenchcapacitor 106, according to some embodiments. In some embodiments,substrate 102 is a dielectric material such as silicon dioxide. In someembodiments, substrate 102 is a semiconductor material. In someembodiments, the substrate 102 is a doped semiconductor material. Viacapacitor 104 extends vertically into substrate 102 of an integratedcircuit. Trench capacitor 106 extend horizontally along a surface ofsubstrate 102. Capacitance of via-shaped capacitors is adjusted bymodifying the size of the via. Via capacitor 104 has an opening 107 withan opening diameter 108, a shaft diameter 110, and a via depth 112. Viasize is adjusted by changing the depth and/or diameter of the via. Viadiameter corresponds to the opening diameter 108 and/or the shaftdiameter 110 of the via. Trench capacitor 106 has a trench depth 114, atrench length 116, and a trench width 118. Trench capacitor 106 has atrench capacitor layout area 120 surrounded by a layout perimeter 122,at least a first distance 124 from the trench opening. Via capacitor 104has a via capacitor layout area 126 surrounded by a layout perimeter 128at least a second distance 130 from via opening 107. Capacitance of viacapacitor 104 is determined by dimensions of the capacitor. Capacitanceof via capacitor 104 is increased by increasing opening diameter 108,shaft diameter 110, and/or depth 112. Capacitance of trench capacitor106 is increased by increasing trench depth 114, trench width 118,and/or trench length 116.

Individual capacitors such as trench capacitor 106 and via capacitor 104have layout areas surrounding them, such as layout area 120 (for trenchcapacitor 106) and layout area 126 (for via capacitor 104). Generally,design rules of an integrated circuit regulate the sizes of and spacingbetween circuit elements, and layout areas included in IC design rulesprovide minimum spacing between capacitors and adjoining features (othercapacitors, as well as wiring and interconnect structures) in order toreduce or control parasitic capacitance, cross talk, and other circuitperformance features. Increasing (or, in some embodiments, decreasing) acapacitor dimension sometimes alters the capacitor layout area. In someembodiments, via capacitor 104 is lengthened (e.g., have a greaterdepth) without modifying the layout area 126 on a top surface ofsubstrate 102. When an opening diameter 108 of via opening 107 isenlarged, layout area 126 increases according to design rules for theintegrated circuit 100. Trench capacitor 106 has layout area 120 thatincreases when trench length 116 and/or trench width 118 increase.Layout area 120 does not increase or decrease when trench depth 114 ismodified because the dimensional change of trench capacitor 106 isperpendicular to the top surface of substrate 102 where layout area 120is located.

One method of increasing capacitance of an integrated circuit capacitor,without merely modifying a dimension of the capacitor, is to change theshape or layout of the capacitor. While modifying trench length 116and/or trench width 118 of trench capacitor 106 modifies thecapacitance, trench capacitor 106 remains a linear trench capacitorafter one or more dimensions are modified. Some embodiments of thepresent disclosure include trench capacitors that have a cross-hatchedshape instead of being linear trench capacitors common to manymanufacturing processes. Cross-hatched shapes of trench capacitorsinclude, in some embodiments, one or more primary trenches extending ina first direction, intersected by one or more secondary trenchesextending in a second direction different from the first direction, suchthat the substrate supporting the cross-hatched trench capacitor hasbeen divided, in a plan view, to form islands or intruding areas. Withinthe layout area of a trench capacitor, inclusion of secondary trencheshas the effect of substantially increasing the surface area within thetrench(es) for receiving conductive layers that serve as capacitorplates. Trench capacitors having a cross-hatched structure use the areawithin the layout area more efficiently than trench capacitors withoutsecondary trenches extending from, or cross-connecting, primarytrenches. In some embodiments, cross-hatched trench capacitors have overtwice the capacitance of linear trench capacitors for the same layoutarea of an integrated circuit.

FIG. 2 is a plan view of an array 200 of linear trench capacitors 202,204, 206, and 208, arranged in parallel in a substrate material andseparated by a design rule separation distance 210, such that eachtrench capacitor of the array 200 has a layout area 212 surrounding thetrench within a layout perimeter 214. A majority of the surface area ofa substrate having the array 200 of linear trench capacitors comprisesempty space surrounding the trenches. Trench capacitors such as trenchcapacitors 202, 204, 206, and 208 are straight, and, for a given trenchsize, maximize the fraction of the layout area that borders trenchesfrom adjoining trenches or other circuit elements.

FIG. 3 is a plan view of a single cross-hatched trench capacitor 300that includes a set of primary trenches 302A-D extending in a firstdirection 301 and a set of secondary trenches 304A-E, extending in asecond direction 303. First direction 301 and second direction 303 areperpendicular in some embodiments. In some embodiments, an angle 305between the first direction and the second direction ranges from about30 degrees to about 150 degrees, although angles outside this range arealso within the scope of this disclosure. Each primary trench ofcross-hatched trench capacitor 300 has a primary trench width 302W and aprimary trench length 302L. Each secondary trench of cross-hatchedtrench capacitor 300 has a secondary trench width 304W and a secondarytrench length 304L. Embodiments of cross-hatched trench capacitors arenot restricted by the particular dimensions or embodiment represented bycross-hatched trench capacitor 300, however; in some embodiments primaryand/or secondary trenches each have different widths and/or differentlengths according to designs of an integrated circuit without adverseeffect on a capacitor function. Further, embodiments of cross hatchedtrench capacitors have different numbers of primary trenches andsecondary trenches than are depicted in FIG. 3. In some embodiments, anumber of primary trenches and/or secondary trenches, and the dimensionsof the trenches (width, length, depth, intersection spacing, or thelike) are adjusted and modified according to an integrated circuitdesign rule in order to meet a desired performance metric whileremaining within the scope of the present disclosure.

Cross-hatched trench capacitor 300 further includes islands (alsoreferred to as pillars) 306 located between intersections of adjoiningprimary trenches and secondary trenches. Island 306A, for example, issituated between primary trenches 302A and 302B, and between secondarytrenches 304A and 304B. Island 306A has an island length 306L and anisland width 306W, where 306W is the distance between adjacent secondarytrenches 304A-B, and 306L is the distance between adjacent primarytrenches 302A-B. In cross-hatched trench capacitor 300, each island 306has a same island area because each primary trench 302 has a sameprimary trench spacing distance 302S, and each secondary trench has asame secondary trench spacing distance 304S. In some embodiments,primary trench spacing and secondary trench spacing are different foreach pair of primary and secondary trenches in a cross-hatched trenchcapacitor without limiting the scope of the present disclosure.

Cross-hatched trench capacitor 300 has a layout area 308 within a layoutarea perimeter 310. An outer edge of cross-hatched trench capacitor 300is separated from layout area perimeter 310 by a design rule separationdistance 312. In some embodiments, design rule separation distance isthe same on all sides of a cross-hatched trench capacitor. In someembodiments, the design rule separation distance is different on some orall sides of the layout area. In some embodiments, a layout area of across-hatched trench capacitor is smaller than the layout area of alinear trench capacitor when the two capacitors have equal capacitance.Integrated circuits having cross-hatched trench capacitors use lesslayout area or perform to a higher standard (e.g., longer charge decaytimes) than integrated circuits having linear trench capacitors. Lineartrench capacitors have elongated layout areas, while cross-hatchedtrench capacitors have shapes with much different “aspect ratios” (i.e.,ratios of the long dimension to the short dimension) and shapes. In someembodiments, a cross-hatched trench capacitor has a square layout areawith an aspect ratio of 1:1 (length:width). Capacitance of a singlecapacitor per unit of layout area increases for cross-hatched trenchcapacitors, as compared to linear trench capacitors, because theless-elongated layout area of a cross-hatched trench capacitor “packs”conductive surface area (e.g., the sidewalls of the primary andsecondary trenches) into the layout area more efficiently than lineartrenches do in linear trench layout areas. A conductive layer used in acapacitor plate extends across sidewalls and a bottom of a trench for atrench capacitor. Cross-hatched structure of trenches increases thesurface area on which conductive layers are deposited (e.g., by usingthe previously unused space between long stretches of primary trenchesto hold short segments of secondary trenches) within a capacitorstructure to increase capacitance or provide greater capacitance perunit of layout area of an integrated circuit.

FIG. 4A depicts an embodiment of an “open layout” cross-hatched trenchcapacitor 400 (also known as a pure open layout cross-hatched trenchcapacitor), according to one or more embodiments. Cross-hatched trenchcapacitor 300 is representative of a “closed layout” capacitor, whereprimary and secondary trenches of the capacitor form sidewalls of thecapacitor in the substrate where the capacitor is formed. In closedlayout capacitors, trench intersections at corners of the capacitor aregenerally “L” shaped, intersections along capacitor sidewalls are “T”shaped, and interior intersections are “X” shaped. In some embodiments,closed layout capacitors have only islands or pillars of substratematerial within a layout area of the capacitor. Cross-hatched trenchcapacitor 400 is representative of an “open layout” capacitor, wheresome trenches, or portions thereof, extend outward past an intersectionwith another trench to form intruding areas of substrate material arounda perimeter of the capacitor into the capacitor area.

Cross-hatched trench capacitor 400 has a single primary trench 402extending along a first direction 408, and three secondary trenches404A-C extending along a second direction 410. For purposes of namingwithin the scope of the present disclosure, primary trenches are thosetrenches with the longest trench length, and those trenches that areparallel with them, and secondary trenches are shorter than the primarytrenches (generally) and at an angle thereto. According to someembodiments, primary trenches and secondary trenches have a same lengthin the substrate. Primary trench 402 has a primary trench length 402Land a primary trench width 402W. Secondary trenches 404A-C have asecondary trench width 404W, and two associated lengths: a totalsecondary trench length 404L1 (measured from a terminal end to a distalend of a secondary trench), and an abbreviated secondary trench length404L2, measuring a protrusion of the secondary trench beyond a sidewallof a primary trench. Intruding areas 406 around cross-hatched trenchcapacitor 400 all have a same area. Intruding areas around other openlayout cross-hatched trench capacitors are all a same size, or each havedifferent sizes, according to the dimensions and locations of thetrenches in the trench capacitors of one or more embodiments. Intrudingarea 406A (bounded on two sides by the trenches of the trench capacitor)has a first intruding area length P1 and a first intruding area width P2and intruding area 406B (bounded on three sides by the trench capacitor)has a second intruding area length P3 and a second intruding area widthP4. The particular embodiments of cross-hatched trench capacitorsincluded herein (e.g., closed layout cross-hatched trench capacitor 300and open layout cross-hatched trench capacitor 400) are two among manycross-hatched trench capacitor structures that are included within thescope of the present disclosure, which may include combinations of“open” and “closed” layout portions on different sides of across-hatched trench capacitor and have at least one island or pillar atan interior of the capacitor, and/or at least one intruding area featureadjoining and outside the capacitor.

FIG. 4B is a plan view of a cross-hatched trench capacitor 440 havingaspects of open and closed layouts as described above. Cross-hatchedtrench capacitor 440 has two primary trenches 442 and 444, intersectedby three secondary trenches 446, 448, and 450. The intersections ofprimary and secondary trenches creates two islands 452A and 452B withincross-hatched trench capacitor 440, surrounded by a plurality ofintruding areas 454A-454F with dimensions regulated by the lengths towhich primary and secondary trenches extend past each other away fromthe islands 442 and 444 at the center region of cross-hatched trenchcapacitor 440. In some embodiments, outer portions of cross-hatchedtrench capacitors are a mixture of islands and intruding areas.

FIG. 5 is a cross-sectional diagram of a trench capacitor 500 embeddedin a substrate 502. Trench capacitor 500 corresponds to thecross-sectional indicator A-A′ of FIG. 3 and to the cross-sectionalindicator D-D′ of FIG. 4A. Aspects of a method 800 of manufacturingtrench capacitor 500 are presented in the flow diagram of FIG. 8 and aredescribed in parallel with the following description of the structure oftrench capacitor 500. Trench capacitor 500 comprises a trench 503Ahaving a trench width W1 and a trench depth H1. Manufacture of trenchcapacitor 500 includes a first operation 810, wherein a trench pattern(also called a capacitor pattern) of the trench capacitor 500 istransferred into a substrate 502. In some embodiments, substrate 502includes one or more semiconductor materials. In some embodiments,substrate 502 includes elementary, or intrinsic, semiconductormaterials, compound semiconductor materials, and/or alloy semiconductormaterials. Examples of elementary semiconductor materials include, butare not limited to, monocrystalline silicon (Si), polycrystallinesilicon (poly-Si), amorphous silicon (a-Si), germanium (Ge), and/ordiamond (C). Binary compound semiconductor materials include, but arenot limited to, IV-IV materials including silicon germanium (SiGe),germanium carbide (GeC), and silicon carbide (SiC), and III-V materialssuch as gallium arsenide (GaAs), gallium phosphide (GaP), indiumphosphide (InP), indium arsenide (InAs), and/or indium antimonide(InSb). Semiconductor materials may also include, but not be limited to,tertiary and quaternary compound semiconductor materials such as GaAsP,AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, although other compoundsemiconductor materials are also envisioned within the scope of thepresent disclosure. In some embodiments, substrate 502 includes one ormore dielectric materials. In some embodiments, substrate materialincludes silicon dioxide, spin-on glass, borophosphosilicate glass(BPSG), fluorinated silica glass (FSG), low-K dielectric materials,silicon-oxy-nitride, of other dielectric material suitable for aninter-layer dielectric, or for forming a capacitor trench therein.

In some embodiments, the layer(s) incorporated in the substrate 502 areformed using a suitable technique or method including, but not limitedto, metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy(MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE),metal-organic molecular beam epitaxy (MOMBE), atomic layer deposition(ALD), and/or combinations thereof.

In some embodiments, the substrate 502 includes both a semiconductormaterial and an insulating material to form a semiconductor-on-insulator(SOI) substrate. According to one or more embodiments, a SOI substrateincludes at least one semiconductor layer formed on top of an insulatingmaterial (dielectric material) that electrically isolated the at leastone semiconductor layer from adjoining semiconductor materials or othercomponents of an integrated circuit, or adjoining integrated circuits,during a manufacturing process. SOI substrates sometimes includedielectric materials such as silicon dioxide or sapphire (e.g.,silicon-on-sapphire (SOS)). Some embodiments of substrate 502 includestrained semiconductor materials and/or epitaxially grown layers topromote carrier mobility in the semiconductor material.

In some embodiments, substrate 502 includes doped semiconductormaterials. Some substrates may include single layers of semiconductormaterials, according to one or more embodiments. Some substrates includemultiple layers of semiconductor materials, according to one or moreembodiments. According to one or more embodiments, dopants in asemiconductor material layer are found in multiple layers of amultiple-layer semiconductor material film stack or are found in asingle layer of a multiple-layer semiconductor material film stack.According to some embodiments, one or more of the semiconductormaterials are doped with at least one p-type and/or n-type dopantdepending on the functional and/or performance target parameters for thesemiconductor devices being manufactured on the substrate.

In some embodiments, operation 810 includes preparatory steps that areconducted before a trench pattern is etched into the substrate.Preparatory steps may include processing steps such as depositing a maskonto a top surface of a substrate in order to control dimensions of thetrench pattern during the etch process. According to some embodiments,mask materials include, but are not limited to, photoresist, polyimide,silicon oxide, silicon nitride (e.g., Si₃N₄), SiON, SiC, SiOC, orcombinations thereof. A mask may include a single layer of material, ormultiple layers of material according to performance specifications ofan integrated circuit and manufacturing processes thereof. In someembodiments, multiple layers of mask material are desirable when aprocess window for making a trench pattern in a substrate exhibitsinstability, when additional etch process selectivity is desired, orwhen a pattern benefits from improved shape control by the use ofadditional mask layers. Precursor steps may also include (when the maskmaterial is not photoresist), depositing photoresist material onto a topsurface of the substrate. In some embodiments, the photoresist materialis a first mask layer. In some embodiments, the photoresist layer is atransitory layer used for transferring a pattern to a mask layer betweenthe photoresist and the substrate. In some embodiments, the mask layeris an inorganic mask layer, comprising a silicon dioxide, siliconnitride, silicon oxy-nitride, or other mask layer capable of beingselectively etched with respect to the substrate material.

In some embodiments, precursor steps include etching the mask layer onthe substrate material before recessing the substrate material byetching a trench into the substrate material. Persons having ordinaryskill in the art will recognize that the scope of suitable techniquesthat are compatible with forming a trench pattern in a substrate areincluded within the scope of the present disclosure and do not constrainthe description of the present disclosure that is included herein.

In operation 810, transferring a trench pattern to the substrate occursby etching the substrate using one or more mask layers on a top surfaceof the substrate. In some embodiments, the etching process is a wetchemical etch process. In some embodiments, the etch process is a dryetch or plasma etch process. The etch process to transfer the trenchpattern to the substrate is selected according to the nature of thesubstrate being etched and to the desired characteristics of the trenchpattern in the substrate. In some embodiments, plasma etching of asubstrate material is performed using halogen-containing reactive gassesstimulated to dissociate into ions by strong electromagnetic fields. Insome embodiments, reactive gasses include CF₄, SF₆, NF₃, C₁₂, CCl₂F₂,SiCl₄, BCl₂, or a combination thereof suitable for etching semiconductorsubstrate material. In some embodiments, reactive gasses include singlegasses and combinations of gases suitable for etching dielectricmaterials into which trenches are being formed. Reactive ions areaccelerated to strike a substrate material by alternatingelectromagnetic fields or by fixed bias according to techniques ofplasma etching known in the art. Wet etching processes include exposureof a masked substrate to aqueous or dissolved etchants such as citricacid (C₆H₈O₇), hydrogen peroxide (H₂O₂), nitric acid (HNO₃), sulfuricacid (H₂SO₄), hydrochloric acid (HCl), acetic acid (CH₃CO₂H),hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoricacid (H₃PO₄), ammonium fluoride (NH₄F) potassium hydroxide (KOH),ethylenediamine pyrocatechol (EDP), TMAH (tetramethylammoniumhydroxide), or a combination thereof. According to some embodiments, acombination of both wet and dry etching processes is used to form atrench pattern in the substrate.

The trench pattern formed in the substrate includes sets of linescorresponding to primary and secondary trenches, according to one ormore embodiments of the present disclosure. The number, spacing,dimensions, and orientation of trench lines in the trench pattern mayvary according to individual integrated circuit design constraints.However, a trench pattern within the scope of the present disclosure isat least described as having one or more primary trenches (see, e.g.,FIG. 3 elements 302A-D, or FIG. 4A element 402) extending in a firstdirection (see, e.g., FIG. 3 element 301, or FIG. 4A element 408) and atleast one secondary trench extending in a second direction (see, e.g.,FIG. 3 element 303, or FIG. 4A element 410) different from the firstdirection. Some embodiments of integrated circuit capacitors withcross-hatched trench patterns include a single primary trench and asingle secondary trench. Some embodiments of integrated circuitcapacitors with cross-hatched trench patterns include multiple parallelprimary trenches and one or more secondary trenches. Some embodiments ofintegrated circuit capacitors with cross-hatched trench patterns includea single primary trench and multiple secondary trenches (see, e.g.,cross-hatched trench capacitor 400). In some embodiments, a spacingbetween primary trenches is uniform throughout the trench pattern. Insome embodiments, spacing between primary trenches is not uniformthroughout the trench pattern. In some embodiments, a protruding portionof a trench portion may extend a different distance from an intersectingtrench in a cross-hatched capacitor pattern than other trench portionsthat also extend from the intersecting trench and extend in the samedirection. In some embodiments, cross-hatched trench patterns mayinclude islands or pillars at an interior of the trench pattern. In someembodiments, cross-hatched trench patterns may include islands orpillars, and also include intruding areas around an exterior portion ofa trench pattern for the capacitor. Subsequent to opening the masklayer(s) and etching the trench into the substrate (whether by wetetching or by dry/plasma etching), one or more mask layers are removedfrom the substrate top surface prior to proceeding with capacitorformation.

Method 800 includes operation 820, wherein alternating layers ofinsulating and conductive materials are deposited, in pairs. In someembodiments, an insulating layer is deposited first. In someembodiments, a conductive layer is deposited first. A pair of layers,one insulating and one conducting, is called a film pair.

In some embodiments, insulating layers are formed by chemical vapordeposition (CVD), atomic layer deposition (ALD), high density plasmaCVD, sputtering, or any other suitable method, including those describedpreviously, or combination of methods, for forming a generally conformaldielectric layer on the exposed surfaces of both the substrate and thetrench sidewalls. In some embodiments, an insulating layer may includesilicon dioxide (SiO₂), silicon nitride, SiON, SiC, SiOC, and/orcombinations thereof. An insulating layer may also include one or moredielectric materials including, but not limited to, hafnium oxide(HfO_(x)), lanthanum monoxide (LaO), aluminum monoxide (AlO), aluminumoxide (Al₂O₃), zirconium monoxide (ZrO), titanium monoxide (TiO),tantalum pentoxide (Ta₂O₅), strontium titanate (SrTiO₃), barium titanate(BaTiO₃), hafnium silicate (HfSiO), lanthanum silicate (LaSiO), aluminumsilicate (AlSiO), hafnium titanate (HfTiO₄) or combinations thereof.

In some embodiments, conductive layers are formed by CVD, ALD, HDPCVD,sputtering, or other suitable methods. Examples of a conductive layermay include polysilicon, metals, metal nitrides, silicides, metalalloys, or other suitable electrically conductive materials orcombinations thereof. In some embodiments, conductive layers includemultiple layers that perform functions additional to conducting/storingelectrical charge. In some embodiments of the present disclosure, a sameconductive layer is used throughout a set of film pairs. In someembodiments of the present disclosure, a same insulating layer is usedthroughout the set of film pairs. In some embodiments, each film pairuses the same conductive material and insulating material. In someembodiments, a set of film pairs uses different conductive materials atdifferent layers in the stack of film pairs. In some embodiments, a setof film pairs uses different insulating materials at different layers inthe stack of film pairs.

In some instances, conductive layers are formed from pure metal layers.In some embodiments, conductive layers include alloys of two or moremetals. In some instances, conductive layers include a metal nitride,and/or metal silicide. Pure metals and alloys of two or more metals areformed from sputtering, atomic layer deposition, CVD, PECVD, or otherdeposition techniques known in the art. In some embodiments, metalsilicide layers are formed by depositing a layer of metal and a layer ofsilicon and annealing the metal/silicon films to mix the two materialsby melting and/or diffusion, forming a new conductive layer. Accordingto some embodiments, a thickness of the conductive films ranges from 200Angstroms (Å) to about 600 Å. In embodiments where the conductive filmis too thick, the capacitance of the capacitor decreases. When theconductive film is too thin, the deposited conductive layer isincreasingly prone to having issues with complete coverage of thedielectric layer. Decreased coverage directly and proportionallydecreases the capacitance of the capacitor.

Trench capacitor 500 includes a plurality of film pairs 507, 511, 515,and 519 layered atop each other. In some embodiments, a trench capacitorincludes two film pairs. In some embodiments, a trench capacitorincludes not more than 12 film pairs. In some embodiments, a liner layeris optionally deposited on the substrate within the opening. Whenpresent, a liner layer separates a substrate from a deposited layer ofthe capacitor when the deposited layer of the capacitor is the same typeof material (e.g., an insulator or a conductor/semiconductor) as thesubstrate. In a non-limiting embodiment, a trench capacitor includes aliner layer comprising titanium nitride, although other liner layermaterials are contemplated, such as tantalum, tantalum nitride, copper,and titanium. FIG. 5, as described below, includes a doped semiconductormaterial as substrate 502, a liner layer 504, and multiple film pairs507, 511, 515, and 519 layered atop each other. In the embodiment ofFIG. 5, the first layer of each film pair (e.g., layers 506, 510, 514,and 518) is a conductive layer, and the second layer of each film pair(e.g., layers 508, 512, 516, and 520) is an insulating layer. In otherembodiments, the liner layer is omitted from the film stack when thesubstrate material and the first-deposited layer in the first film pairare opposite types of films (e.g., dielectric substrate, first-depositedlayer is a conductive layer). In some embodiments, the film pairsinclude a first-deposited insulator layer and a second-depositedconductive layer. In some embodiments, liner layer 504 is a diffusionbarrier material. In some embodiments, liner layer 504 is an insulatingmaterial that electrically isolates a semiconductor substrate from afirst-deposited conductive layer in a film pair. In the embodiment ofFIG. 5, liner layer 504 is an insulating liner layer, separating aconductive layer 506 from a doped semiconductor material in substrate502. In some embodiments, the substrate in an insulator material, theliner layer is omitted, and the film pairs are deposited directly ontothe substrate material, with a conductive layer being deposited firstand an insulator layer being deposited second.

Conductive layers of film pairs are formed into capacitor plates of anintegrated circuit capacitor when connected, via a contact plug or someother interconnect structure, to an electrode within an integratedcircuit. In some embodiments, a number (N) of film pairs, or a number(N) of insulating layers and conductive layers, ranges from at least 2to not more than 20, although larger numbers of film pairs are alsoenvisioned within the scope of the present disclosure. In someembodiments, a thickness of insulating layers and conductive layers in atrench capacitor film stack is uniform throughout the film stack. Insome embodiments, the thickness of insulating and conductive layers in atrench capacitor film stack is variable across a wafer, or within astack of films in a capacitor, according to a capacitance specificationof an integrated circuit. In some embodiments, each of the conductivelayers has a thickness of about 200 Å to about 600 Å. In someembodiments, certain of the conductive layers have a different thicknessfrom at least one of the conductive layers meeting or exceeding apredetermined minimum design thickness. In some embodiments, each of theconductive layers has a thickness of about 400 Å to about 450 Å. In someembodiments, prior to deposition of any insulating or conductive layerin a trench, a liner layer 504 is deposited in order to isolate thesubstrate material (doped, or undoped) from the trench capacitor filmstack.

In some embodiments method 800 further includes an operation 825, aconductive layer trimming step, wherein a layer of conductive materialis covered with a layer of photoresist or some other masking materialand etched to leave behind a remaining portion of conductive materialthat covers the bottom and sides of trench 503A and a portion of the topside 502 t of substrate 502 or, a top side 504 t of liner material 504.Optionally, subsequent to trimming the conductive material, a sealingmaterial 523 is deposited onto the top surface of the conductivematerial to protect an end portion of the conductive material (or theconductive layer 506, 510, 514, and/or 518). Subsequent to trimming ofthe conductive material, insulating material for insulating layers 508,512, 516, and/or 520 is deposited onto the top surface of conductivematerial in a conductive layer (and a portion of the sealing material,if present), and the insulating material is also trimmed to form a filmpair with a portion of the insulating material extending over anentirety of the top surface of a conductive layer on which theinsulating material is deposited, and a portion of the sealing materialat an end of each conductive layer. In some instances, a sealingmaterial is an insulating material similar to the materials used forinsulating layers, as described above in operation 825.

When multiple film pairs are deposited into a trench, the first filmpair has a largest lateral spread on a top surface of the substrate 502or liner 504, and each successive film pair has a smaller lateralspread. The reduction in lateral spread of the conductive layer andinsulating layer in successive, or later-deposited, film pairs providesa lateral area or contact pad portion of the earlier-depositedconductive films, to which electrical contact is made using a via orconductive pillar formed through a later-deposited inter-layerdielectric material on top of the trench capacitor. The size andlocation of the lateral area of each conductive layer or film pair isdetermined during the trimming process. In some embodiments, the contactpad for one film pair or conductive layer is disposed at one end of thetrench capacitor, and the contact pad for an adjoining film pair isdisposed at a different end of the trench capacitor, to reduce alikelihood of accidental short misconnection of the vias extendingthrough the ILD. In some embodiments, a single conducive layer hasmultiple contact pads, each contact pad being connected by avia/interconnect to a same charging line of the capacitor.

Method 800 may include optional operation 830, depositing, on at least atop-most insulating layer of the stack of insulating and conductivelayers in film pairs, a filling insulator layer 522. Filling insulatorlayer 522 in FIG. 5 is deposited onto insulating layer 520 when a topsurface of insulating layer 520 on one side of the trench is separatedfrom a top side of insulating layer 520 on the other side of the trench.In some instances, a trench capacitor has two film pairs than are shownin FIG. 5. In some instances, a trench capacitor has not more than 12film pairs.

Filling insulator layer 522 separated the top surface of insulatinglayer 520 on each side of the trench from the portion on the other sideand provides structural stability for the film pairs deposited into thetrench pattern. Filling insulator layer 522 includes one or more ofSiNx, SiOx, SiON, SiC, SiCN, BN, SiBN, SiCBN or other dielectricmaterials suitable for filling an opening between portions of thetop-most film pair on each side of the trench from the segment on theother side of the trench.

Method 800 includes an operation 840 in which top portion conductivelayers, such as at the contact pads, as described above, are exposed formaking electrical connections to portions of the integrated circuit. Insome embodiments, prior to forming contact openings and exposing part ofthe contact pads, insulating and etch stop layers are deposited on topof film pairs and the filling insulating material 522.

Thus, in some embodiments, trench capacitor 500 includes a contact etchstop layer (CESL) 524 deposited over the substrate, the liner layer (ifpresent), and the film pairs, and a second etch stop layer 526 toprotect the CESL when forming contact plugs. Trench capacitor 500 alsoincludes an inter-layer dielectric (ILD) 528 to isolate the capacitorfrom a remainder of the integrated circuit interconnects. As illustratedin FIG. 5, CESL 524 covers the filling insulating layer 522, and theinsulating layers on top of each film pair and/or the contact pads ofeach film pair. CESL 524 comprises one or more layers of suitable etchstop materials including, but not limited to, SiNx, SiOx, SiON, SiC,SiCN, BN, SiBN, SiCBN, or combinations thereof. In some embodiments, theCESL 524 is formed by chemical vapor deposition (CVD), plasma-enhancedchemical vapor deposition (PE-CVD), physical vapor deposition (PVD),atomic layer deposition (ALD), spin-on coating, other suitable formationprocess(es), or combinations thereof. In some embodiments, a barrier orsecond etch stop layer 526 is deposited on top of CESL 524 in order topromote uniform etching of an inter-layer dielectric (ILD) 528 on top ofthe second etch stop layer. A second etch stop layer is used in someembodiments when the different chemical composition of the second etchstop layer improves selectivity of an etch process to the etch stopmaterial during an etching process to reduce a risk of accidentallyetching through a conductive layer during manufacturing processes. Etchstop layers are also selected to provide spectroscopic endpoints and/orsufficient etch time to clear the contact plug bottom of residualpolymer or ILD material and reduce likelihood of blocked etches or smallcontact openings to conductive layers in a trench capacitor. Suitablematerials for a second etch stop layer may include, SiNx, SiOx, SiON,SiC, SiCN, BN, SiBN, SiCBN, or combinations thereof, or other materialsknown in the art.

In some embodiments, electrical connection to another portion of theintegrated circuit is performed using a contact (metal filled into acontact plug opening), or a via, through an inter-layer dielectric (ILD)528 on top of second etch stop layer 526, a second mask layer 532 on topof ILD 528, and electrodes 534 and 536 that extend through second masklayer 532 and rest on ILD 528. In some embodiments, electrodes 534 and536 rest on top of second mask layer 532 and are separated from ILD 528.Electrode 534 is electrically connected to conductive layer 510 bycontact 530A, and to conductive layer 518 by contact 530C. Electrode 536is electrically connected to conductive layer 514 by contact 530B, andto conductive layer 506 by contact 530D. Electrodes 534 and 536 arewithin ILD 538 on top of second mask layer 532. An etch process to formopenings into which contacts 530A-D are formed etches through ILD 528,second etch stop layer 526, contact etch stop layer 524, and aninsulating layer.

In some embodiments, a CESL is formed by chemical vapor deposition(CVD), plasma-enhanced chemical vapor deposition (PE-CVD), physicalvapor deposition (PVD), atomic layer deposition (ALD), spin-on coating,other suitable formation process(es), or combinations thereof. In someembodiments, operation 840 includes depositing a second etch stop layersuch as second etch stop layer 526, as described above. A second etchstop layer is formed by chemical vapor deposition (CVD), plasma-enhancedchemical vapor deposition (PE-CVD), physical vapor deposition (PVD),atomic layer deposition (ALD), spin-on coating, other suitable formationprocess(es), or combinations thereof, using materials as describedabove. Operation 840 includes deposition of an ILD 528 to separateelectrodes 534 and 536 from the top surface of the conductive layers ofthe trench capacitor. ILD 528 is formed by chemical vapor deposition(CVD), plasma-enhanced chemical vapor deposition (PE-CVD), physicalvapor deposition (PVD), atomic layer deposition (ALD), spin-on coating,other suitable formation process(es), or combinations thereof, and mayinclude, but not be limited to, SiNX, SiO_(x), SiON, SiC, SiCN, BN,SiBN, SiCBN, borophosphosilicate glass (BPSG), tetraethyl orthosilicate(TEOS), spin on glass (SOG), undoped silicate glass (USG), fluorinatedsilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhancedTEOS (PETEOS) or combinations thereof. Operation 840 may includedepositing a second mask layer 532 on top of ILD 528. In someembodiments, the second mask layer 532 is deposited by chemical vapordeposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD),physical vapor deposition (PVD), atomic layer deposition (ALD), spin oncoatings, or other methods know in the art. Second mask layer 532 mayinclude insulating films such as silicon oxide, silicon nitride (e.g.,Si₃N₄), SiON, SiC, SiOC, or combinations thereof. Operation 840 includesprocessing steps directed toward forming a pattern, using a mask layersuch as photoresist, on a top surface of ILD 528 or second mask layer532, for contact plug openings in the ILD, and etching at least the ILD528, second etch stop layer 526 (if present), and CESL 524 to expose topportions of conductive films (see conductive films 508, 512, 516, and520 of FIG. 5) through the contact plug openings (not shown, butcorresponding to the positions of contact plugs 532A-D of FIG. 5).

The method 800 includes operation 850, wherein an interconnect structureis connected to the conductive plates of the trench capacitor. Aninterconnect structure includes at least contact plugs (see contactplugs 530A-D and electrodes 534 and 536 of FIG. 5). In some instances,contact plugs are formed in contact plug openings (not shown) by fillingthe contact plug opening formed in operation 840 with a conductivecontact material. Conductive contact material is a single layer ofmaterial, or a plurality of layers of conductive materials conducive tothe filling of contact plug openings with conductive materials. In someembodiments, conductive contact material includes a liner material toprevent diffusion of metal from within the contact plug into the ILDwhere the contact plug is situated. In some embodiments, conductivecontact material includes a metal, a metal nitride, a silicide, or someother conductive material. Examples of conductive contact materialsinclude copper, aluminum, tungsten, titanium, ruthenium, cobalt, andalloys thereof, and another suitable conductive material known in theart. In some instances, conductive contact materials are deposited intocontact plug openings by plating, PVD, sputtering, or any other suitableformation process. Conductive contact materials may include seed layersand barrier layers that are conducive to forming void-free contacts.Conductive contact materials may include materials that are processed(annealed, or implanted, or sputtered) to reduce contact resistance inthe interconnect structure.

Some embodiments of operation 850 include processing steps related toremoving from a top layer of ILD 528 or from second mask layer 532, aremainder of conductive contact material outside of the contact plugs inILD 528. Removal of a remainder of such conductive contact material canbe performed by CMP polishing, wet etching, plasma etching, or acombination thereof, according to techniques known in the art. Operation850 may include processing steps such as depositing a second ILD (suchas ILD 538), depositing photoresist, patterning the photoresist,depositing a second mask material, and etching the second ILD to formopenings for electrodes that connect to contact plugs in connection withconductive layer of a trench capacitor.

FIG. 6 is a cross-sectional view of a trench capacitor 600 having across-hatched structure (corresponding to a trench capacitor 300 alongcross-sectional indicator B-B′ of FIG. 3 or to the trench capacitor 400along cross-sectional indicator D-D′ of FIG. 4A). Numerals of FIG. 6correspond to like numerals of FIG. 5, incremented by 100 for clarity todescribe similar structural elements, materials used, and manufacturingmethods for making similar trench capacitors. Trench capacitor 600 has aplurality of trenches, including trench 603A and 603B. Trench 603A has adepth AH1 and a width AW1, and trench 603B has a depth BH2 and a widthBW2. A separation width 605 is a distance between nearest sidewalls oftrenches 603A and 603B. A first electrode 634 is electrically connectedto a first conductive layer 608 by a contact plug 630A, and to a thirdconductive layer 616 by a contact plug 630C. A second electrode 636 iselectrically connected to a second conductive layer 612 by a contactplug 630B, and to a fourth conductive layer 620 by a fourth contact plug630D. A trench capacitor with a cross-hatched structure such ascapacitor 600 can physically (laterally) separate electrodes thatcontact different layers of the film pairs/conductive layers in thetrenches. In some embodiments, one of the electrodes of a capacitor withcross-hatched structure are connected to the substrate by a groundingcontact plug (not shown) in order to discharge residual carriers from acapacitor, or to ground one plate prior to charging the capacitor,preventing “floating” charge from disrupting the performance of thecapacitor in an integrated circuit.

FIG. 7A is a plan view of a capacitor 700 having a recessed field 702.Recessed field 702 has a field length 702L in a first direction 703, anda field width 702W in a second direction 704. Field width 702W issmaller than field length 702L. Recessed field 702 is broken up by threeislands 705A-C. Each island 705 has an island length 705L in the firstdirection and an island width 705W in the second direction. Each islandis separated from an adjoining island by an inter-island separationdistance 712, and from a sidewall of the recessed field 702 byseparation distances 706, 708, and 710. In some embodiments, a ratio ofthe field width 702W and the island width 705W is about 3:1 (althoughratios greater than 3:1 are also envisioned by the present disclosure),where the recessed field 702 includes trenches on opposite sides of theislands 705. In some embodiments, a ratio of the field width and islandwidth is greater than 10:1, where the recessed field on each side of theislands is wider than it is deep, and the islands break up a broadrecessed area with sidewall surface area on which conductive layers of acapacitor are deposited. In some embodiments, the separation distance710 and the inter-island separation distance 712 are smaller than theisland length 705L. In some embodiments, the separation distance and theinter-island separation distance are larger than the island length 705L.Islands 705 are included within recessed field 702 to provide additionalsurface area (on the sidewalls thereof, in addition to the sidewalls ofthe recessed field, and the flat area at the bottom of the recessedfield) for capacitor plates. In some instances, a recessed field has afixed field length and field width, and a surface area of a capacitorplate is modified by adding a plurality of islands with sidewalls fordeposition of layers of conductive material for the capacitor plates.

FIG. 7B is a plan view of a capacitor 720 having a recessed field 721filled with a plurality of islands 727, where the islands are rounded.In some embodiments, islands are elliptical. In some embodiments,islands are circular. In some embodiments, rounded islands 727 areseparated from sidewalls of recessed field 721 by separation distances725 (between an island and a short sidewall of recessed field 721) and724 (between an island and a long sidewall of recessed field 721). Insome embodiments, islands 727 are separated by an inter-islandseparation distance 726. In some embodiments, separation distance 726 issmaller than separation distances 724 and 725. Islands 727 withinrecessed field are present to provide additional sidewall area (inaddition to the sidewalls of the recessed field, and the flat bottomareas of the recessed field) for capacitor plates (e.g., the conductivelayers deposited over the substrate to store charge for the capacitor).

FIG. 9 is a cross sectional diagram of a capacitor 900 embedded in asubstrate 903, having a recessed field 903 with a field depth 903D, atotal field width 903W1 (extending between sidewalls of the recessedfield 903), and a “half” field width 903W2 extending from one sidewall905 to a sidewall 904S of an island 904 in the recessed field. Island904 is a reduced-height island (also known as a reduced-height pillar).A reduced-height island has a height less than the height of a sidewallof the recessed field in which the reduced height island is located(e.g., island height 904H is less than field depth 903D). Island 904 hasan island width 904W. A liner layer 906 is formed, according totechniques described above, on the substrate 902, and extendscontinuously over the sides and bottom of the recessed field 903, andover the sides and top of the island 904. In some embodiments, linerlayer is omitted from the structure. Insulating layer 908 has beendeposited, according to techniques described above, on the substrate(or, optionally the liner layer), and continuously covers the sides andbottom of the recessed field 903, and over the sides and top of theisland 904. Conductive layer 910 has been deposited, according totechniques described above, onto insulating layer 908. Insulating film912 has been deposited onto conductive layer 910, and conductive layer914 has been deposited onto insulating film 912. Insulating layers 908and 912, and conductive layers 910 and 914 extend continuously over thesidewalls and bottom of recessed field 903, and over the sidewalls 904Sand top 904T of island 904. Insulating filler 916 has been deposited ontop of conductive layer 914 within the recessed field 903, and thedevice has undergone planarization such that a top surface 902T of thesubstrate is substantially parallel with a top surface 916T of theinsulating filler 916. Edge portions of conductive layers 910 and 914are also substantially planar with top surfaces 916T and 902T. In someembodiments, island height 904H is equal to field depth 903D, such thatplanarization of the device results in a cross-sectional diagramresembling that shown in FIG. 6, where two trenches appear to beisolated (as along cross-sectional line B-B′ or D-D′) from each other byan intervening substrate pillar or island. According to someembodiments, a height 904H of island 904 is adjusted duringmanufacturing in order to adjust a capacitance of capacitor 900.

A structure for trench capacitors includes trenches extending in twodirections, where space between primary trenches extending in a firstdirection is partially filled with secondary trenches extending in thesecond direction. By repurposing the space between primary trenches,formerly used to isolate adjoining capacitors, to storing charge,overall capacitance of a cross-hatched structure trench capacitorbecomes greater (per unit of layout area of an integrated circuit) thanfor purely linear trench capacitors. Greater capacitance per unit layoutarea allows manufacturers to reduce die area, or to increase a number ofcapacitors in an integrated circuit, for similar manufacturing cost,increasing profitability. Cross-hatched structure trench capacitors arecapable of fine adjustments to capacitance within a given layout area bymodifying spacing between trenches, or by modifying island sizes withinthe capacitor layout area, at no additional cost (in terms of layoutarea), simplifying circuit design processes.

Some embodiments of methods for manufacturing a capacitor include theoperations of etching a plurality of primary trenches into a firstregion of a substrate, with each of the primary trenches extending in afirst direction, etching a plurality of secondary trenches into thefirst region of the substrate, with each of the secondary trenchesextending in a second direction other than the first direction, withadjacent secondary trenches of the plurality of secondary trenches andadjacent primary trenches of the plurality of primary trenches jointlydefine an island, etching the island to recess an upper surface of theisland relative to an upper surface of a second region of the substrate,with the second region of the substrate surrounding the first region ofthe substrate, depositing a first dielectric layer into each of theprimary trenches, into each of the secondary trenches, and on theisland, and depositing a first conductive layer on the first dielectriclayer.

Some embodiments of methods for manufacturing a capacitor include one ormore additional operations selected from a list including forming afirst dielectric layer having a first dielectric top surface that issubstantially parallel to a top surface of the substrate, forming asecond dielectric layer having a second dielectric top surface that issubstantially parallel to the top surface of the substrate, forming afirst capacitor plate having a first capacitor plate top surface that issubstantially parallel to the top surface of the substrate, forming asecond capacitor plate having a second capacitor plate top surface thatis substantially parallel to the top surface of the substrate, extendinga portion of the first capacitor plate along a sidewall of the island,arranging each of the plurality of primary trenches to be perpendicularto each of the plurality of secondary trenches, forming a secondconductive layer, wherein the first and second conductive layerscollectively form the first capacitor plate, forming third and fourthconductive layers, with the third and fourth conductive layerscollectively forming the second capacitor plate, arranging each of thesecondary trenches having a distal end opening into a first primarytrench of the plurality of primary trenches and a proximal end openinginto a second primary trench of the plurality of primary trenches,wherein each of the plurality of secondary trenches has a length equalto a minimum distance between the first and secondary primary trenchesof the plurality of primary trenches, arranging each of the secondarytrenches having a distal end extending beyond a first primary trench ofthe plurality of primary trenches and a proximal end extending beyond asecond primary trench of the plurality of primary trenches, wherein eachof the plurality of secondary trenches has a length greater than adistance between the first and secondary primary trenches of theplurality of primary trenches, depositing a plurality of film pairs onthe first conductive layer, each film pair of the plurality of filmpairs including a single dielectric layer and a single conductive layer,establishing a first contact to the single conductive layer for a firstset of the plurality of film pairs, establishing a second contact to thesingle conductive layer for a second set of the film pairs, wherein noneof the single conductive layers is common to both the first set of theplurality of film pairs and the second set of the plurality of filmpairs, and/or patterning a first interconnection structure in electricalcontact with both the first contact and the second contact.

Some embodiments of methods for manufacturing a capacitor include theoperations of applying, a capacitor pattern to a substrate, thecapacitor pattern being a cross-hatched pattern, recessing the substrateto a first depth using the capacitor pattern as an etch mask, to form arecessed portion of the substrate, and depositing, within the recessedportion of the substrate, a plurality of film pairs, each film pair ofthe plurality of film pairs comprising an insulating layer and aconductive layer.

Some embodiments of methods for manufacturing a capacitor include one ormore additional operations selected from a list including depositing aninter-layer dielectric material on the substrate and the plurality offilm pairs within the recessed portion, exposing, with openings throughthe inter-layer dielectric material, a conductive layer of at least twofilm pairs of the plurality of film pairs, filling the openings throughthe inter-layer dielectric material with a conductive contact material,depositing an electrode material on a top surface of the inter-layerdielectric material and the conductive contact material, and/orseparating a first portion of the electrode material from a secondportion of the electrode material.

Some embodiments of methods for manufacturing a capacitor include theoperations of applying a capacitor pattern to a substrate, the capacitorpattern including an island pattern, etching the substrate to a firstdepth using the capacitor pattern as an etch mask to form a plurality oftrenches that define an island structure, recessing an upper surface ofthe island structure relative to an upper surface of the substrate, anddepositing a plurality of film pairs on the trenches and the islandstructure, wherein each film pair of the plurality of film pairsconsists of an insulating layer and a conductive layer.

Some embodiments of methods for manufacturing a capacitor include one ormore additional operations selected from a list including arranging afirst pair of trenches to cross a second pair of trenches to form theisland structure having a rectangular shape, arranging a first subset oftrenches to cross a second subset of trenches to form a plurality ofisland structures including the island structure, establishing a firstelectrical contact with a first subset of the plurality of film pairs,the first subset including a first film pair and each additionalodd-numbered film pair of the plurality of film pairs, establishing asecond electrical contact with a second subset of the plurality of filmpairs, the second subset including a second film pair and eachadditional even-numbered film pair of the plurality of film pairs,recessing an upper surface of the island structure relative to an uppersurface of the substrate by a distance at least equal to a cumulativethickness of the plurality of film pairs deposited on the trenches andthe island structure, recessing an upper surface of the island structurerelative to an upper surface of the substrate by a distance less than acumulative thickness of the plurality of film pairs on the trenches andthe island structure, depositing an inter-layer dielectric material onthe substrate and the plurality of film pairs, etching the inter-layerdielectric material to form openings exposing a conductive layer of atleast two film pairs of the plurality of film pairs, filling theopenings through the inter-layer dielectric material with a conductivecontact material, depositing an electrode material on a top surface ofthe inter-layer dielectric material and the conductive contact material,and/or separating a first portion of the electrode material from asecond portion of the electrode material.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of manufacturing a capacitor comprising:etching a plurality of primary trenches into a first region of asubstrate, each of the primary trenches extending in a first direction;etching a plurality of secondary trenches into the first region of thesubstrate, each of the secondary trenches extending in a seconddirection other than the first direction, wherein adjacent secondarytrenches of the plurality of secondary trenches and adjacent primarytrenches of the plurality of primary trenches jointly define an island;etching the island to recess an upper surface of the island relative toan upper surface of a second region of the substrate, wherein the secondregion of the substrate surrounds the first region of the substrate;depositing a first dielectric layer into each of the primary trenches,into each of the secondary trenches, and on the island; and depositing afirst conductive layer on the first dielectric layer.
 2. The method ofmanufacturing a capacitor according to claim 1, further comprising:forming a first dielectric layer having a first dielectric top surfacethat is substantially parallel to a top surface of the substrate;forming a second dielectric layer having a second dielectric top surfacethat is substantially parallel to the top surface of the substrate;forming a first capacitor plate having a first capacitor plate topsurface that is substantially parallel to the top surface of thesubstrate; and forming a second capacitor plate having a secondcapacitor plate top surface that is substantially parallel to the topsurface of the substrate.
 3. The method of manufacturing a capacitoraccording to claim 2, further comprising: extending a portion of thefirst capacitor plate along a sidewall of the island.
 4. The method ofmanufacturing a capacitor according to claim 1, further comprising:arranging each of the plurality of primary trenches to be perpendicularto each of the plurality of secondary trenches.
 5. The method ofmanufacturing a capacitor according to claim 2, further comprising:forming a second conductive layer, wherein the first and secondconductive layers collectively form the first capacitor plate.
 6. Themethod of manufacturing a capacitor according to claim 5, furthercomprising: forming a third conductive layer; and forming a fourthconductive layer, wherein the third and fourth conductive layerscollectively form the second capacitor plate.
 7. The method ofmanufacturing a capacitor according to claim 1, further comprising:arranging each of the secondary trenches having a distal end openinginto a first primary trench of the plurality of primary trenches and aproximal end opening into a second primary trench of the plurality ofprimary trenches, wherein each of the plurality of secondary trencheshas a length equal to a minimum distance between the first and secondaryprimary trenches of the plurality of primary trenches.
 8. The method ofmanufacturing a capacitor according to claim 1, further comprising:arranging each of the secondary trenches having a distal end extendingbeyond a first primary trench of the plurality of primary trenches and aproximal end extending beyond a second primary trench of the pluralityof primary trenches, wherein each of the plurality of secondary trencheshas a length greater than a distance between the first and secondaryprimary trenches of the plurality of primary trenches.
 9. The method ofmanufacturing a capacitor according to claim 1, further comprising:depositing a plurality of film pairs on the first conductive layer, eachfilm pair of the plurality of film pairs including a single dielectriclayer and a single conductive layer; establishing a first contact to thesingle conductive layer for a first set of the plurality of film pairs;and establishing a second contact to the single conductive layer for asecond set of the film pairs, wherein none of the single conductivelayers is common to both the first set of the plurality of film pairsand the second set of the plurality of film pairs.
 10. The method ofmanufacturing a capacitor according to claim 9, further comprising:patterning a first interconnection structure in electrical contact withboth the first contact and the second contact.
 11. A method of making acapacitor, comprising: applying, a capacitor pattern to a substrate, thecapacitor pattern being a cross-hatched pattern; recessing the substrateto a first depth using the capacitor pattern as an etch mask, to form arecessed portion of the substrate; and depositing, within the recessedportion of the substrate, a plurality of film pairs, each film pair ofthe plurality of film pairs comprising an insulating layer and aconductive layer.
 12. The method of claim 11, further comprising:depositing an inter-layer dielectric material on the substrate and theplurality of film pairs within the recessed portion; and exposing, withopenings through the inter-layer dielectric material, a conductive layerof at least two film pairs of the plurality of film pairs.
 13. Themethod of claim 12, further comprising: filling the openings through theinter-layer dielectric material with a conductive contact material;depositing an electrode material on a top surface of the inter-layerdielectric material and the conductive contact material; and separatinga first portion of the electrode material from a second portion of theelectrode material.
 14. A method of making a capacitor, comprising:applying a capacitor pattern to a substrate, the capacitor patternincluding an island pattern; etching the substrate to a first depthusing the capacitor pattern as an etch mask, to form a plurality oftrenches that define an island structure; recessing an upper surface ofthe island structure relative to an upper surface of the substrate; anddepositing a plurality of film pairs on the trenches and the islandstructure, wherein each film pair of the plurality of film pairsconsists of an insulating layer and a conductive layer.
 15. The methodof making a capacitor according to claim 14, further comprising:arranging a first pair of trenches to cross a second pair of trenches toform the island structure having a rectangular shape.
 16. The method ofmaking a capacitor according to claim 14, further comprising: arranginga first subset of trenches to cross a second subset of trenches to forma plurality of island structures including the island structure.
 17. Themethod of making a capacitor according to claim 14, further comprising:establishing a first electrical contact with a first subset of theplurality of film pairs, the first subset including a first film pairand each additional odd-numbered film pair of the plurality of filmpairs; and establishing a second electrical contact with a second subsetof the plurality of film pairs, the second subset including a secondfilm pair and each additional even-numbered film pair of the pluralityof film pairs.
 18. The method of making a capacitor according to claim14, further comprising: recessing an upper surface of the islandstructure relative to an upper surface of the substrate by a distance atleast equal to a cumulative thickness of the plurality of film pairsdeposited on the trenches and the island structure.
 19. The method ofmaking a capacitor according to claim 14, further comprising: recessingan upper surface of the island structure relative to an upper surface ofthe substrate by a distance less than a cumulative thickness of theplurality of film pairs on the trenches and the island structure. 20.The method of claim 14, further comprising: depositing an inter-layerdielectric material on the substrate and the plurality of film pairs;etching the inter-layer dielectric material to form openings exposing aconductive layer of at least two film pairs of the plurality of filmpairs; filling the openings through the inter-layer dielectric materialwith a conductive contact material; depositing an electrode material ona top surface of the inter-layer dielectric material and the conductivecontact material; and separating a first portion of the electrodematerial from a second portion of the electrode material.